1. Field of the Invention
The present invention pertains to a method for testing a substrate which is provided with a wiring structure, in particular, a chip in accordance with the introductory clause of claim 1, a solder-deposit carrier in accordance with the introductory clause of claim 11 which can be used with this method, and a solder deposit in accordance with the introductory clause of claim 19, which can be used on the solder-deposit carrier.
2. Discussion of the Related Art
The manufacture of an IC that is assembly-ready, such as is used in electronic devices for EDP for example, is divided into a large number of manufacturing steps from a wafer to an encased, assembly-ready chip.
Apart from the costs that are caused by the manufacturing of the wafer, the costs for the manufacturing of an assembly-ready, packaged chip are primarily caused by the subsequent manufacturing steps. These steps are primarily the creation of so-called bumps on the bond pads of the chips, which are created from the wafer by singling them out, and the expensive packaging of the chips. As a rule, for the quality control of the chips, an electrical check of the chip's strip conductors is carried out after the chip has been encased. Many times, however, the causes for the malfunctioning of a chip have their base in one of the manufacturing steps which precede the packaging of the chip, so that faulty chips which represent rejects even before the encasing, are packaged unnecessarily. As a result, the costs associated with what will be a reject in any case are increased even further.
Even in the so-called "flip-chip technology" in which chips are bonded directly to a substrate by means of increased contact metallization applied to the chip bond pads, a quality control check of the chips, or even of the complete wafers that are used in the flip-chip process, is not carried out until after the production of the connection. Overall, the processing of chips or complete wafers by means of the flip-chip method leads to complex structures which do not allow for the complete testability of individual chips or complete wafers under defined test conditions, such as are prescribed for a burn-in test, for example, without risk to the entire structure when using known test methods.
While it is indeed known in the art to check individual chips or even complete wafers with appropriate test devices before carrying out a subsequent connecting technique, a quality check of such a type can only be carried out, however, with exceptional effort, which is in addition to the carrying out of the connecting technique which is already complex in itself.